Translation lookaside buffer management
https://doi.org/10.21122/2309-4923-2019-4-20-24
Abstract
This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification.
About the Author
Y. I. Klimiankou
Belarusian State University of Informatics and Radioelectronics
Belarus
Software Engineer
Belarus
Software Engineer
References
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Review
For citations:
Klimiankou Y.I. Translation lookaside buffer management. «System analysis and applied information science». 2019;(4):20-24. https://doi.org/10.21122/2309-4923-2019-4-20-24
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